View MT44H8M32F1FW-16_3906815.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef808f8a4f gddr3_1.fm - rev. a 6/03 en 1 ?2003 micron technology, inc. 256mb: x32 gddr3 sdram advance ? graphics ddr3 sdram mt44h8m32 ? 2 meg x 32 x 4 banks for the latest data sheet, please refer to the micron web site: www.micron.com/datasheets features ?v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v single ended read strobe (rdqs) per byte single ended write strobe (wdqs) per byte internal, pipelined double-data-rate (ddr) architecture; two data accesses per clock cycle calibrated output drive differential clock inputs (ck and ck#) commands entered on each positive ck edge rdqs edge-aligned with data for reads wdqs center-aligned with data for writes four internal banks for concurrent operation data mask (dm) for masking write data 4 n prefetch programmable burst lengths: 4 and 8 32ms, 4k-cycle auto refresh auto precharge option auto refresh and self refresh modes 1.8v pseudo open drain logic i/o concurrent auto precharge support t ras lockout support on-die termination (odt) programmable write la tency (1, 2, 3, or 4) figure 1: fbga package part number example mt44h8m32f2fw-16 note: due to space limitations, fbga-packaged components have an abbreviated part mark that is different from the part number. see our web site for more information on abbre- viated component marks. options marking configuration 8 meg x 32 (2 meg x 32 x 4 banks) 8m32 ck and ck# on-die termination enabled 1,2 note: 1. odt values subject to change. 2. contact micron for availability. f1 disabled f2 package 12mm x 13mm 135-ball fbga fw timing ? cycle time 600 mhz @ cl = 8 -16 550 mhz @ cl = 7 -18 500 mhz @ cl = 6 -2 table 1: addressing 8 meg x 32 configuration 2 meg x 32 x 4 banks refresh count 4,096 row addressing 4,096 (a0?a11) bank addressing 4 (ba0, ba1) column addressing 512 (a0?a7,a9) table 2: key timing parameters cl = cas (read) latency speed grade clock rate cl = 8 cl = 7 cl = 6 cl = 5 -16 600 mhz 550 mhz 500 mhz 450 mhz -18 ? 550 mhz 500 mhz 400 mhz -2 ? ? 500 mhz 400 mhz
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_1.fm - rev. a 6/03 en 2 ?2003 micron technology, inc. general description the 256mb (x32) graphics ddr3 (gddr3) dram is a high-speed cmos, dynamic random access memory containing 268,435,456 bits. it is internally configured as a quad-bank dram. the 256mb gddr3 sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 4 n - prefetch architecture with an interface designed to transfer four data bits every two clock cycles at the i/o pins. a single read or write access for the 256mb gddr3 sdram effectively consists of a single 4 n -bit- wide, data transfer at the internal dram core. the single-ended write data strobes (wdqs 0?3) are transmitted externally, along with data, for use in data capture at the gddr3 sdram input receiver. wdqs is center-aligned with data for writes. the read data is transmitted by the gddr3 sdram edge- aligned to the read strobes (rdqs 0?3). the 256mb gddr3 sdram operates from a differ- ential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on first rising edge of wdqs after the one-half cycle write preamble, and output data is referenced on the first rising edge of rdqs after the one-half cycle read preamble. read and write accesses to the gddr3 sdram are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a specified sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the gddr3 sdram provides for programmable read or write burst lengths of four and eight locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdr sdrams, the pipelined, multibank architecture of gddr3 sdrams allows for concurrent operation, thereby providing high, effec- tive bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power-saving power-down mode. note: throughout the data sheet, the various fig- ures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dqs collectively, unless specifically stated other- wise.
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3toc.fm - rev. a 6/03 en 3 ?2003 micron technology, inc. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 cas latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 write latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 programmable impedance output buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 dll enable/disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 vendor id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 data termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 on die termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 mirror function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 bank/row activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 power-down (cke not active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 current states for truth tables: table 9 and table 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 row active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 same-bank noninterruptible states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 precharging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 row activating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 read with auto precharge enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 write with auto precharge enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 noninterruptible states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 refreshing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 accessing mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 precharging all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 read or write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3lof.fm - rev. a 6/03 en 4 ?2003 micron technology, inc. list of figures figure 1: fbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: functional block diagram (8 meg x 32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 3: 135 fbga ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 4: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 5: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: write latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 7: extended mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 8: data termination disable timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 9: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 10: example: meeting t rcd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 11: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 12: read burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 13: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 14: non-consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 15: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 16: read to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 17: read to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 18: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 19: write burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 20: consecutive write to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 21: nonconsecutive write to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 22: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 23: write to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 24: write to read with data masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 25: write to read?odd number of data masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 26: write to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 27: write to precharge ? with data masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 28: write to precharge ? odd number of data masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 29: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 30: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 31: v dd q input voltage waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 32: tc test point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 33: clock input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 34: derating data valid window ( t qh - t dqsq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 35: pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 36: pull-up characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 37: active termination characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 38: data output timing ? t dqsq, t qh, and data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 39: data output timing ? t ac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 40: data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 41: initialize and load mode registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 42: power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 43: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 44: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 45: bank read without auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 46: bank read with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 47: bank write without auto precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 48: bank write with auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 49: write ? dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 figure 50: 135-ball fbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3lot.fm - rev. a 6/03 en 5 ?2003 micron technology, inc. list of tables table 1: addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: 135 ball/pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6: truth table ? commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 7: truth table 2 ? dm operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 8: truth table ? cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 table 9: truth table ? current state bank n ? command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 10: minimum delay between commands to different ba nks with auto precharge enabled . . . . . . . . .43 table 11: truth table ? current state bank n ? command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 12: dc electrical characteristics and operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 13: ac input operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 table 14: thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 15: clock input operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 16: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 17: i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 18: electrical characteristics and ac operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 19: programmed drive characteristics at 40 table 20: programmed drive characteristics at 60 for active termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 6 ?2003 micron technology, inc. figure 2: functional block diagram (8 meg x 32) 12 ras# cas# row- address mux ck cs# we# ck# control logic column- address counter/ latch mode registers 9 command decode a0?a11, b a0, ba1 mf res cke 12 address register 14 512 (x128) 65,536 i/o gating dm mask logic column decoder bank0 memory array (4,096 x 512 x 32) bank0 row- address latch and decoder 4,096 sense amplifiers bank control logic 14 bank1 bank2 bank3 12 7 2 2 refresh counter 32 32 32 rcvrs 128 128 128 ck out data zq clk ck/ck# col0, col1 col0, col1 ck in clk drvrs dll mux 32 32 32 32 32 dq(0?31) dm(0?3) 4 read latch write fifo and drivers data 32 32 32 32 128 4 4 4 4 mask 4 4 4 4 4 16 32 32 2 bank1 bank2 bank3 input registers wdqs(0?3) 4 rdqs(0?3) rdqs(0?3) rdqs generator
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 7 ?2003 micron technology, inc. table 3: 135 ball/pin descriptions fbga ball-out symbol type description j6, h6 ck, ck# input clock: ck and ck# are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. g2 cke input clock enable: cke high activates and cke low deactivates the internal clock, input buffers, and output drivers. taking cke low provides precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for power-down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit and for disabling the outputs. cke must be main- tained high throughout read and write accesses. input buffers (excluding ck, ck#, and cke) are disabled during power- down. input buffers (excluding cke) are disabled during self refresh. f10 cs# input chip select: cs# enables (registered low) and disables (regis- tered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. g1, f2, g10 ras#, cas#,we# input command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. d4, d8, m8, m4 dm0?dm3 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on the rising and falling edges of wdqs. f1, f11 ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. h(1, 2, 10, 11), j(1?4, 8?11) a0?a11 input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a8) for read/ write commands, to select one location out of the memory array in the respective bank. a8 sampled during a precharge command determines whether the precharge applies to one bank (a8 low, bank selected by ba0, ba1) or all banks (a8 high). the address inputs also provide the op-code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode register) is loaded during the load mode register command. a2?4, b2?4, c2, d3, dq0?7 i/o data input/output: bidirectional data bus. a8?10, b8?10, c10, d9 dq8?15 i/o data input/output: bidirectional data bus. m9, n10, p8?10, r8?10 dq16?23 i/o data input/output: bidirectional data bus. m3, n2, p2?4, r2?4 dq24?31 i/o data input/output: bidirectional data bus. c3, c9, n8, n4 rdqs(0?3) output read data strobe: output with read data. rdqs is edge-aligned with read data. c4, c8, n9, n3 wdqs(0?3) input write data strobe: input with write data. wdqs is center- aligned to the input data. k(1, 2, 10, 11),g11 nc/rfu reserved for future use. a(1, 11), c(1, 11), e(1, 2, 10, 11), f(4, 8), k(4, 8), l(1, 2, 10, 11), n(1, 11), r(1, 11) v dd q supply dq power supply: +1.8v 0.1v. isolated on the die for improved noise immunity.
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 8 ?2003 micron technology, inc. note: 1. rfu pins not listed may also be reserved for other uses now or in the future. this table simply defines specific rfu pins deemed to be of importance. b(1, 11), d(1, 2, 10, 11), f(3, 9), e(3, 4, 8, 9), m(1,2,10,11), l(3, 4, 8, 9), p(1, 11), k(3,9) v ss q supply dq ground: isolated on the die for improved noise immunity. b6, c6, h(4, 8), n6, p6, r6 v dd supply power supply: +1.8v 0.1v. d6, e6, g6, k6, l6 v ss supply ground. g(4, 8) v ref supply reference voltage. g(3, 9) v dd a supply dll power supply. h(3, 9) v ss a supply dll ground. f6 mf reference mirror pin. a6 zq reference external reference pin for the output drive. m6 res input reset pin. table 3: 135 ball/pin de scriptions (continued) fbga ball-out symbol type description
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 9 ?2003 micron technology, inc. figure 3: 135 fbga ballout note: rfu pins not listed may also be reserved for other uses now or in the future. this table simply defines specific rfu pins deemed to be of importance. v dd q dq0 dq1 zq dq9 dq8 v dd q v ss q v ss q v ss q dq2 dq3 v dd dq11 dq10 v ss qv ss q v ss q v dd q v dd q rdqs0 wdqs0 v dd wdqs1 rdqs1 v dd q v dd q v ss qv ss q dq4 dq5 v ss dq13 dq12 v ss qv ss q v dd qv dd q dq6 dq7 v ss dq15 dq14 v dd qv dd q ba0 cas# v ss q dm0 mf dm1 v ss q cs# ba1 ras# cke v dd a v ref v ss v ref v dd a we# rfu a3 a1 v ss a vdd ck# v dd v ss a a5 a9 a11 a10 a2 a0 ck a4 a6 a8 a7 rfu rfu v ss q dm3 vss dm2 v ss q rfu rfu v dd qv dd q dq25 dq24 vss dq16 dq17 v ss q v ss q v ss qv ss q dq27 dq26 res dq18 dq19 v dd q v dd q v dd q v ss q wdqs3 rdqs3 v dd rdqs2 wdqs2 v ss q v ss q v ss q v dd q dq29 dq28 v dd dq20 dq21 v dd q v dd q v dd q v ss q dq31 dq30 v dd dq22 dq23 v ss q v dd q 1 2 3 4 6 8 9 10 11 a b c d e f g h j k l m n p r
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 10 ?2003 micron technology, inc. functional description the 256mb gddr3 sdram is a high-speed cmos, dynamic random access memory containing 268,435,456 bits. the 256mb gddr3 sdram is inter- nally configured as a quad-bank dram. the 256mb gddr3 sdram uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 4 n - prefetch architecture, with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 256mb gddr3 sdram consists of a 4 n data transfer every two clock cycles at the internal dram core and four correspond- ing n -bit-wide, one-half-clock-cycle data transfers at the i/o pins. read and write accesses to the gddr3 sdram are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a11 select the row). the address bits registered coincident with the read or write command are used to select the starting col- umn location for the burst access. prior to normal operation, the gddr3 sdram must be initialized. the following sections provide detailed information covering device initialization, register def- inition, command descriptions, and device operation. initialization gddr3 sdrams must be powered up and initial- ized in a predefined manner. operational procedures other than those specified may result in undefined operation. power must first be applied to v dd and v dd q simultaneously, and then to v ref . v ref can be applied any time after v dd q. inputs are not recog- nized as valid until after v ref is applied. once power has been applied, the gddr3 device requires 100s for the power supplies to stabilize before the res pin tran- sitions to high. upon power-up, the on-die termina- tion value for the address and control pins will be set, based on the state of cke when the res pin transitions from low to high. the on-die termination for ck and ck# will also be set for the t1 version of the die at this time. on the rising edge of res, the cke pin is latched to determine the on-die termination value for the address and control lines. in a single-rank system, cke is sampled at a logic low with the on-die termi- nation set to one-half of zq, and for a dual-rank sys- tem, cke is sampled logic high to set the on-die termination to the same value as zq. cke must meet t ats and t ath on the rising edge of res to set the on- die termination for either a single- or dual-rank sys- tem. once t ath is met, cke needs to be brought low while the on-die termination and output drivers cali- brate. res must be maintained at a logic low level value during the first stage of power-up to ensure that the dq outputs will be in a predefined state, where they will remain until the res pin is brought high. after the res pin is brought high, all outputs will be pulled high by the on-die termination until driven by a read command. after all power supplies and reference voltages are stable, and the clock is stable, the gddr3 sdram requires a 200s delay prior to applying an executable command. once the 200s delay has been satisfied, a dese- lect or nop command should be applied, cke should be brought high, followed by a nop com- mand, and a precharge all command should be applied. next, a load mode register command should be issued for the extended mode register (ba1 low and ba0 high) to activate the dll and set oper- ating parameters, followed by a load mode regis- ter command (ba0/ba1 both low) to reset the dll and to program the rest of the operating parameters. 200 clock cycles are required between the dll reset and any read command to allow the dll to lock for micron?s device. the standard requires 20k clock cycles. a precharge all command should then be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed to update the driver impedance and calibrate the output drivers. following these requirements, the gddr3 sdram is ready for normal operation. mode register definition the mode register is used to define the specific mode of operation of the gddr3 sdram. this defini- tion includes the selection of a burst length, cas latency, write latency, and operating mode, as shown in figure 4, mode register definition, on page 11. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit a8, which is self-clearing).
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 11 ?2003 micron technology, inc. figure 4: mode register definition reprogramming the mode register will not alter the contents of the memory. the mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent opera- tion. violating either of these requirements will result in unspecified operation. mode register bits m0?m2 specify the burst length; m3 specifies the type of burst (sequential); m4?m6 specify the cas latency; m7 is a test mode; m8 speci- fies the operating mode; and m9?m11 specify the write latency. burst length read and write accesses to the gddr3 sdram are burst-oriented, with the burst length being program- mable, as shown in figure 4, mode register definition. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 4 or 8 locations are available for the sequential burst type. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a2?a i when the burst length is set to four and by a3?a i when the burst length is set to eight (where a i is the most significant column address bit for a given configuration). the remaining (least signifi- cant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst must be programmed to be sequential; this is referred to as the burst type and is selected via bit m3. this device does not support the interleaved burst mode found in ddr sdram devices. the ordering of accesses within a burst is deter- mined by the burst length, the burst type, and the starting column address, as shown in table 4: burst definition. table 4: burst definition burst 1 , 2 length note: 1. for a burst length of four, a2 ? a7 select the block of four burst; a0?a1 select the starting column within the block and must be set to zero. 2. for a burst length of eight, a3 ? a7 select the of eight burst; a0?a2 select th e starting column within the block. starting column address order of accesses within a burst type = sequential 4 a1 a0 0 0 0-1-2-3 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 1 0 0 4-5-6-7-0-1-2-3 reserved reserved 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll 0 1 0 1 burst type sequential reserved cas latency 8 reserved reserved reserved reserved 5 6 7 burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0* 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 0 1 test normal test mode m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m8 om tst wl a10 a11 ba0 ba1 10 11 12 13 * m12 and m13 (ba0 and ba1) must be ?0, 0? to select the base mode register (vs. the extended mode register). write latency reserved 1 2 3 4 reserved reserved reserved m9 0 1 0 1 0 1 0 1 m10 0 0 1 1 0 0 1 1 m11 0 0 0 0 1 1 1 1
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 12 ?2003 micron technology, inc. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the latency can be set to 5?8 clocks, as shown in figure 5, cas latency, on page 12. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . table 6 indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. write latency the write latency (wl) is the delay, in clock cycles, between the registration of a write command and the availability of the first bit of input data as shown in figure 6. the latency can be set from 1 to 4 clocks depending on the operating frequency and desired current draw. when the write latencies are set to 1 or 2 clocks, the input receivers never turn off, in turn, rais- ing the operating power. when the write latency is set to 3 or 4 clocks the input receivers turn on when the write command is registered. if a write command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . reserved states should not be used as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by issuing a mode register set command with bit a8 set to zero, and bits m0?m6 and m9?m11 set to the desired values. a dll reset is initiated by issuing a mode register set command with bit a8 set to one, and bits m0?m7 and m9?m11 set to the desired values. all other combinations of values for m7?m11 are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future ver- sions may result. figure 5: cas latency table 5: cas latency allowable operating frequency (mhz) speed cl = 8 cl = 7 cl = 6 -16 600 550 500 -18 - 550 500 -2 - - 500 read nop nop nop note: 1. burst length = 4 in the cases shown. 2. shown with nominal t ac and nominal t dsdq. ck ck# command dq rdqs cl = 8 t0 t6 t7 t8 t8n don?t care transitioning data ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) read nop nop nop ck ck# command dq rdqs cl = 5 t0 t3 t4 t5 t5n ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 13 ?2003 micron technology, inc. figure 6: write latency extended mode register the extended mode register controls functions beyond those controlled by the mode register; these additional functions are dll enable/disable, drive strength, data termination, vendor id, and low-power mode. these functions are controlled via the bits shown in figure 7, extended mode register definition. the extended mode register is programmed via the load mode register command to the mode regis- ter (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. the enabling of the dll should always be followed by a load mode register command to the mode register (ba0/ba1 both low) to reset the dll. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiat- ing any subsequent operation. violating either of these requirements could result in unspecified operation. figure 7: extende d mode register definition note: 1. e12 and e13 (ba0 and ba1) must be ?1, 0? to select the extended mode register (vs. the base mode register). 2. reserved for future use. set values to ?0.? programmable impedance output buffer the gddr3 sdram uses a programmable imped- ance output buffer. this enables a user to match the driver impedance to the system. to adjust the imped- ance, an external precision resistor (rq) is connected between the zq pin and v ss . the value of the resistor must be six times the desired driver impedance. for example, a 240 resistor is required for an output impedance of 40 . to ensure that output impedance is one-sixth the value of rq (within 10 percent), the range of rq is 210 to 270 (35 ?45 output imped- ance). res, ck and ck# are not internally terminated. ck and ck# need to be terminated on the system using external one percent resistors to v dd for the t2 version of the die. the t1 version of the die includes the on-die termination on ck and ck# and is set to the same value as the address and control pins. the output impedance is updated during all auto refresh commands to compensate for variations in supply voltage and temperature. the output imped- ance updates are transparent to the system. imped- ance updates do not affect device operation, and all data sheet timing and current specifications are met during an update. write nop nop nop note: 1. burst length = 4 in the cases shown. 2. shown with nominal t ac and nominal t dsdq. ck ck# command dq wl = 4 t0 t2 t3 t4 t4n don?t care transitioning data ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) write nop nop nop ck ck# command dq wdqs wl = 3 t0 t1 t2 t3 t3n ( ) ( ) ( ) ( ) wdqs ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 0 1 dll enable disable 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 654 3 8 2 1 0 e6 0 1 low power disable enable e11 a10 a11 ba1 ba0 10 11 12 13 ds 0 1 vendor id disable enable e10 rfu 2 rfu 2 data termination off reserved 1/4 zq 1/2 zq e2 0 1 0 1 e3 0 0 1 1 drive strength auto cal reserved reserved reserved e0 0 1 0 1 e1 0 0 1 1 data t dll v lp
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 14 ?2003 micron technology, inc. the device will power up with an output impedance set at 40 . to guarantee optimum output driver impedance after power-up, the gddr3 sdram needs 350 cycles after the clock is applied and stable to cali- brate the impedance. the user can operate the part with fewer than 350 clock cycles, but optimal output impedance is not guaranteed. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after dis- abling the dll for debugging or evaluation. (when the device exits self refresh mode, the dll is enabled auto- matically.) any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. low-power mode the low-power mode is set through bit e11 in the extended mode register. when e11 = 1 during the emrs command the gddr3 power-down mode uses less power but takes more time to exit power-down. this mode of operation requires 10 clock cycles to exit power down in comparison to the four cycles needed during normal operation.
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 15 ?2003 micron technology, inc. vendor id the vendor id (v) is selected through bit e10 in the extended mode register. when bit e10 = 1 during an emrs command the gddr3 device will drive the ven- dor id on dq [0:3] and the die revision on dq [4:7]. the id code will start to drive x clocks, where x equals the set cas latency plus two clocks, after the emrs command is initiated through bit e10 and continue to drive the code until another emrs command is issued with the e10 bit set to ?0.? after the e10 bit is set to ?0,? the dq pins will stop driving x clock cycles after the emrs command, where x equals burst length times two. the vendor id for micron is 0xf, and the die revi- sion for the this device is 0xf. data termination the data termination value is used to define the value for the on-die termination for the dq, dm, and wdqs pins. the gddr3 device supports one-quarter zq and one-half zq termination for a nominal 60 or 120 set with bit e3 and e2 during an emrs command for a single- or dual-loaded system.
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 16 ?2003 micron technology, inc. commands table 6 provides a quick reference of available commands, followed by a description of each com- mand. two additional truth tables appear following the operation section; these tables provide current state/next state information. note: 1. cke is high for all commands shown except self refresh. 2. ba0?ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 select extended mode register; other comb inations of ba0?ba1 are reserved). a0?a11 provide the op- code to be written to the selected mode register. 3. ba0?ba1 provide bank address and a0?a11provide row address. 4. ba0?ba1 provide bank address; a0?a7 and a9 provide colu mn address; a8 high enables the auto precharge feature (nonpersistent), and a8 low disables the auto precharge feature. 5. a8 low: ba0?ba1 determine which bank is precharged. a8 high: all banks are precharged and ba0?ba1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. deselect and nop are functionally interchangeable. 9. used to mask write data; provided coincident with the corresponding data. 10.used for bus snooping when the dq termination is set to 120 ohms in the emr and cannot be used during power-down or self refresh. table 6: truth table ? commands note: 1 name (function) cs# ras# cas# we# addr notes deselect (nop) hxxx x 8 no operation (nop) l hhh x 8 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) l h l h bank/col 4 write (select bank and column, and start write burst) l h l l bank/col 4 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (enter self refresh mode) lllh x 6, 7 load mode register l l l l op-code 2 data terminator disable xhl h x 10 table 7: truth table 2 ? dm operation name (function) dm dqs notes write enable lvalid9 write inhibit hx9
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 17 ?2003 micron technology, inc. deselect the deselect function (cs# high) prevents new commands from being executed by the gddr3 sdram. the gddr3 sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected gddr3 sdram to perform a nop (cs# low). this prevents unwanted commands from being registered during idle or wait states. opera- tions already in progress are not affected. load mode register the mode registers are loaded via inputs a0?a11. see mode register descriptions in the register defini- tion section. the load mode register command can only be issued when all banks are idle, and a sub- sequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a pre- charge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a7, a9 selects the starting column location. the value on input a8 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a7, a9 selects the starting column loca- tion. the value on input a8 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is regis- tered low, the corresponding data will be written to memory; if the dm signal is registered high, the cor- responding data inputs will be ignored and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise, ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a pre- charge command will be treated as a nop if there is no open row in that bank (idle state) or if the previ- ously open row is already in the process of precharg- ing.
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 18 ?2003 micron technology, inc. auto precharge auto precharge is a feature that performs the same individual-bank precharge function described above but without requiring an explicit command. this is accomplished by using a8 to enable auto precharge in conjunction with a specific read or write com- mand. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initi- ated at the earliest valid stage within a burst. this ?ear- liest valid stage? is determined as if an explicit precharge command was issued at the earliest pos- sible time, without violating t ras min , as described for each burst type in the operation section of this data sheet. the user must not issue another command to the same bank until the precharge time ( t rp) is com- pleted. auto refresh auto refresh is used during normal operation of the gddr3 sdram and is analogous to cas#- before-ras# (cbr) refresh in fpm/edo drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an auto refresh command. the 256mb x32 gddr3 sdram requires auto refresh cycles at an average interval of 7.8s (maximum). a maximum of eight auto refresh commands can be posted to any given gddr3 sdram, meaning that the maximum absolute interval between any auto refresh command and the next auto refresh command is 9 x 7.8s (70.2s). this maxi- mum absolute interval allows gddr3 sdram output drivers to automatically recalibrate to compensate for voltage and temperature changes. self refresh the self refresh command can be used to retain data in the gddr3 sdram, even if the rest of the sys- tem is powered down. when in the self refresh mode, the gddr3 sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is dis- abled (low). the dll is automatically disabled upon entering self refresh and is automatically enabled and reset upon exiting self refresh. the on-die ter- mination is also disabled upon entering self refresh except for cke and enabled upon exiting self refresh. (two hundred clock cycles must then occur before a read command can be issued.) input signals except cke are ?don?t care? during self refresh. the procedure for exiting self refresh requires a sequence of commands. first, ck and ck# must be stable prior to cke going back high. once cke is high, the gddr3 sdram must have nop commands issued for t xsnr because time is required for the com- pletion of any internal refresh in progress. a simple algorithm for meeting both refresh and dll require- ments and output calibration is to apply nops for 200 clock cycles before applying any other command to allow the dll to lock and the output drivers to recali- brate. if the gddr3 device enters self refresh with the dll disabled the gddr3 device will exit self refresh with the dll disabled. on die termination bus snooping for read commands other than cs# is used to control the on-die termination in the dual load configuration. the gddr3 sdram will disable the on-die termination when a read command is detected, regardless of the state of cs#, when the odt for the dq pins are set for dual loads (120 ).the on- die termination is disabled x clocks after the read command where x equals cl - 1 and stay off for a dura- tion of bl + 2, as shown in figure 8, data termination disable timing, on page 19. in a two-rank system, both dram devices snoop the bus for read com- mands to either device and both will disable the on-die termination if a read command is detected. the on- die termination for all other pins on the device are always on for both a single-rank system and a dual- rank system. the on-die termination value on address and con- trol pins is determined during power-up in relation to the state of cke on the first transition of res. on the rising edge of res, if cke is sampled low, then the configuration is determined to be a single-rank sys- tem. the on-die termination is then set to one-half zq for the address pins. on the rising edge of res, if cke is sampled high, then the configuration is deter- mined to be a dual-bank system. the t1 version of the die also sets the on-die termination to the ck and ck# pins at this time to the same value as the address and control pins. the on-die termination is then set to zq for the address pins. the on-die termination for the dqs, wdqs, and dm pins is set in the emr.
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 19 ?2003 micron technology, inc. mirror function the gddr3 sdram provides a mirror function (mf) ball to change the physical location of the control lines and all address lines assisting in routing devices back to back. the mf ball will affect ras#, cas#, we#, cs#, and cke on balls g1, f2, g10, f10, and g2, respectively and a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, ba0, and ba1 on balls j4, h2, j3, h1, j8, h10, j9, j11, j10, h11, j2, j1, f1, and f11, respectively, and will only detect a dc input. the mf ball should be tied directly to v ss or v dd , depending on the control line orientation desired. the mirror function is only sup- ported on the 135-ball package. when the mf ball is tied low, the ball orientation is as follows: ras# - g1, cas# - f2, we# - g10, cs# - f10, cke - g2, a0 - j4, a1 - h2, a2 - j3, a3 - h1, a4 - j8, a5 - h10, a6 - j9, a7 - j11, a8 - j10, a9 - h11, a10 - j2, a11 - j1, ba0 - f1, and ba1 - f11. the high condition on the mf ball will change the location of the control balls as follows: ras# - g11, cas# - f10, we# - g2, cs# - f2, cke - g10, a0 - j8, a1- h10, a2 - j9, a3 - h11, a4 - j4, a5 - h2, a6 - j3, a7 - j1, a8 - j2, a9 - h1, a10 - j10, a11 - j11, ba0 - f11, and ba1 - f1. figure 8: data termination disable timing note: 1. do n = data-out from column n . 2. burst length = 4. 3. three subsequent elements of data-out appear in the specified order following do n . 4. shown with nominal t ac and t dqsq. 5. rdqs will start driving high one-half cloc k cycle prior to the first falling edge. 6. the data terminators are disabled starting at cl - 1 and the duration is bl + 2. 7. reads to either rank disable both ranks? termination regardless of the logic level of cs#. ck ck# command read nop nop nop nop nop address bank a, col n cl = 8 dq dq termination rdqs do n t0 t7 t8 t9 t8n t9n t10 t11 don?t care transitioning data ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) gddr3 data termination is disabled
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 20 ?2003 micron technology, inc. operations bank/row activation before any read or write commands can be issued to a bank within the gddr3 device, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated, as shown in figure 9, acti- vating a specific row in a specific bank. after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. t rcd min should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 16ns with a 450 mhz clock (2.2ns period) results in 7.2 clocks rounded to 8. this is reflected in figure 10, example: meeting t rcd, which covers any case where 7 < t rcd min / t ck 8. the same procedure is used to convert other specification limits from time units to clock cycles). a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the mini- mum time interval between successive active com- mands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access over- head. the minimum time interval between successive active commands to different banks is defined by t rrd. figure 9: activating a specific row in a specific bank figure 10: example: meeting t rcd cs# we# cas# ras# cke a0?a11 ra ra = row address ba = bank address high ba0, 1 ba ck ck# command ba0, ba1 act act nop t rrd t rcd ck ck# bank x bank y a0?a11 row row nop rd/wr nop bank y col nop t0 t1 t2 t3 t4 t7 t8 t9 don?t care nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 21 ?2003 micron technology, inc. reads read bursts are initiated with a read command, as shown in figure 11. the starting column and bank addresses are pro- vided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst after t ras min has been met. for the generic read commands used in the following illustrations, auto precharge is dis- abled. during read bursts, the valid data-out element from the starting column address will be available fol- lowing the cas latency after the read command. each subsequent data-out element will be valid nomi- nally at the next positive or negative strobe edges. figure 12, shows general timing for two of the possible cas latency settings. the gddr3 sdram drives the output data edge-aligned to the crossing of ck and ck# and to rdqs. the initial high transitioning low of rdqs is known as the read preamble; the half cycle coincident with the last data-out element is known as the read postamble. upon completion of a burst, assuming no other commands have been initiated, the dqs will go to v dd do to the on-die termination. a detailed explanation of t dqsq (valid data-out skew), t dv (data-out window hold), and the valid data window are shown in figure 38. a detailed explanation of t ac (dqs and dq transition skew to ck) is shown in figure 39 on page 56. data from any read burst may be concatenated with data from a subsequent read command. a con- tinuous flow of data can be maintained. the first data element from the new burst follows the last element of a completed burst. the new read command should be issued x cycles after the first read command, where x equals 2 x the number of data element nibbles (nibbles are required by the 4 n -prefetch architecture) depending on the burst length. this is shown in figure 13, consecutive read bursts, on page 23. non- consecutive read data is shown in figure 14. full- speed, random read accesses within a page (or pages) can be performed as shown in figure 15, random read accesses, on page 25. data from a read burst cannot be terminated or truncated. during read commands the gddr3 sdram dis- ables its on-die termination when data is valid on the bus. figure 11: read command cs# we# cas# ras# cke ca a0?a7, a9 a8 ba0, 1 high en ap dis ap ba a10, a11 ck ck# ca = column address ba = bank address en ap = enable auto precharge dis ap = disable auto precharge don?t care
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 22 ?2003 micron technology, inc. figure 12: read burst note: 1. do n = data-out from column n . 2. burst length = 4. 3. three subsequent elements of data-out appear in the specified order following do n . 4. shown with nominal t ac and t dqsq. 5. rdqs will start driving high one-half cloc k cycle prior to the first falling edge. ck ck# command read nop nop nop nop nop address bank a, col n read nop nop nop nop nop bank a , col n cl = 8 ck ck# command address dq rdqs cl = 5 dq rdqs do n do n t0 t3 t4 t5 t5n t6n t6 t7 t0 t7 t8 t9 t8n t9n t10 t11 don?t care transitioning data ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 23 ?2003 micron technology, inc. figure 13: consecutive read bursts note: 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. three subsequent elements of data-out ap pear in the programmed order following do b . 5. shown with nominal t ac, and t dqsq. 6. example applies only when read commands are issued to same device. 7. rdqs will start driving high one half clock cycle prior to the first falling edge of rdqs. ck ck# command read nop nop nop address bank, col n bank, col b command read read nop nop nop address bank, col n bank, col b cl = 8 ck ck# command address dq rdqs cl = 5 dq rdqs do n do b do n do b t0 t2 t7 t8 t8n t9 t10 t9n t10n t0 t2 t4 t5 t5n t6 t7 t6n t7n don?t care transitioning data ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) read nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 24 ?2003 micron technology, inc. figure 14: non-consecutive read bursts note: 1. do n (or b ) = data-out from column n (or column b ). 2. burst length = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. three subsequent elements of data-out ap pear in the programmed order following do b . 5. shown with nominal t ac and t dqsq. 6. example applies when read commands are issued to different devices or nonconsecutive reads. 7. rdqs will start driving high one -half clock cycle prior to the first falling edge of rdqs. ck ck# command read nop nop nop nop nop address bank, col n read bank, col b command address cl = 8 ck ck# command address dq rdqs cl = 5 dq rdqs do n t0 t7 t8 t9 t8n t9n t10 t17 t17n t18 read nop nop nop nop nop bank, col n read bank, col b t0 t3 t4 t5 t5n t6 t5 t9n t10 do b do n do b don?t care transitioning data ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 25 ?2003 micron technology, inc. figure 15: random read accesses note: 1. do n (or x or b or g ) = data-out from column n (or column x or column b or column g ). 2. burst length = 4. 3. reads are to an active row in any bank. 4. shown with nominal t ac and t dqsq. 5. rdqs will start driving high one -half clock cycle prior to the first falling edge of rdqs. bank, col x command address ck ck# command address dq rdqs cl = 5 do n do n+3 do n+1 do x do n+2 do x+ read nop read nop nop bank, col n nop t0 t1 t2 t5 t5n t6 t7 t6n t7n command address ck ck# command address dq rdqs cl = 8 do n do n+3 do n+1 do x do n+2 do x+1 read read nop nop bank, col n t0 t1 t2 t8 t8n t9 t10 t9n t10n don?t care transitioning data nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) bank, col x ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 26 ?2003 micron technology, inc. figure 16: read to write note: 1. do n = data-out from column n . 2. di b = data-in from column b . 3. burst length = 4. 4. three subsequent elements of data-out ap pear in the programmed order following do n . 5. data-in elements are applied following di b in the programmed order. 6. shown with nominal t ac and t dqsq. 7. t dqss in nominal case. 8. rdqs will start driving high one-half clock cycl e prior to the first falling edge of rdqs. ck ck# command read nop write nop address bank, col n nop bank, col b t0 t7 t8 t9 t8n t10 t11 t9n t11n wdqs cl = 8 dq rqds dm di b don?t care transitioning data do n ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop t wl = 3 ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 27 ?2003 micron technology, inc. figure 17: read to precharge note: 1. do n = data-out from column n . 2. burst length = 4. 3. three subsequent elements of data-out ap pear in the programmed order following do n . 4. shown with nominal t ac and t dqsq. 5. read to precharge equals two clocks, which enables two data pairs of data-out. 6. pre = precharge command; act = active command. 7. rdqs will start driving high one-half clock cycl e prior to the first falling edge of rdqs. ck ck# command 6 read nop pre nop nop act address bank a , col n bank a , ( a or all ) bank a , row read nop pre nop nop act bank a , col n t rp t rp ck ck# command 6 address dq rdqs cl = 5 dq rdqs do n do n t0 t1 t2 t5 t5n t6 t7 t8 t0 t1 t2 t8 t9n t8n t9 t10 bank a , ( a or all ) bank a , row don?t care transitioning data nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) cl = 8
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 28 ?2003 micron technology, inc. writes write bursts are initiated with a write command, as shown in figure 18, write command. the starting column and bank addresses are pro- vided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered on a rising edge of wdqs following the write latency set in the mode register, and subse- quent data elements will be registered on successive edges of wdqs. prior to the first valid wdqs edge, a half cycle is needed and specified as the write pre- amble. there cannot be a low-to-high transition in the half cycle before the preamble; the half cycle on wdqs following the last data-in element is known as the write postamble and must be driven high by the controller. it cannot be left to float high using the on- die termination. the time between the write command and the first valid edge of wdqs ( t dqss) is specified relative to the write latency (wl - 0.25ck and wl + 0.25ck). all of the write diagrams show the nominal case, and where the two extreme cases (i.e., t dqss min and t dqss max ) might not be intuitive, they have also been included. figure 19, write burst, shows the nominal case and the extremes of t dqss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dqs terminate and any addi- tional input data will be ignored. data for any write burst cannot be truncated with a subsequent write command. the new write com- mand can be issued on any positive edge of clock fol- lowing the previous write command, assuming the previous burst has completed. the new write com- mand should be issued x cycles after the first write command, where x equals the number of desired nib- bles x2 (nibbles are required by 4 n -prefetch architec- ture). an example of nonconsecutive writes is shown in figure 21 on page 31. full-speed, random write accesses within a page or pages can be performed as shown in figure 22 on page 32. data for any write burst may be followed by a sub- sequent read command. to follow a write, t wtr should be met as shown in figure 23, write to read, on page 33. data for any write burst cannot be truncated by a subsequent read command. data for any write burst may be followed by a sub- sequent precharge command, but t wr needs to be met as shown in figure 26, write to precharge, on page 36. data for any write burst cannot be truncated by a subsequent precharge command. after the pre- charge command, a subsequent command to the same bank cannot be issued until t rp is met. figure 18: write command cs# we# cas# ras# cke ca a8 ba0, 1 high en ap dis ap ba ck ck# ca = column address ba = bank address en ap = enable auto precharge dis ap = disable auto precharge don?t care a0?a7, a9 a10, a11
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 29 ?2003 micron technology, inc. figure 19: write burst note: 1. di b = data-in for column b . 2. three subsequent elements of data-in are a pplied in the specified order following di b . 3. a burst of 4 is shown. 4. a8 is low with the write command (auto precharge is disabled). 5. write latency is set to 4. t dqss (max) t dqss (nom) t dqss (min) dm dq ck ck# command write address bank a , col b nop nop nop nop nop nop t0 t1 t2 t3 t3n t4n t4 t5 t6 t5n wdqs wdqs wdqs t dqss dm dq t dqss dm dq di b di b don?t care transitioning data t dqss di b
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 30 ?2003 micron technology, inc. figure 20: consecutive write to write note: 1. di b , etc. = data-in for column b , etc. 2. three subsequent elements of data-in are a pplied in the specified order following di b . 3. three subsequent elements of data-in are a pplied in the specified order following di n . 4. burst of 4 is shown. 5. each write command may be to any bank of the same device. 6. write latency is set to 3. ck ck# command write nop write nop nop address nop nop bank, col b bank, col n t0 t1 t2 t3 t4 t5 t4n wdqs t3n t6 t7 t6n t5n dq dm di n di b don?t care transitioning data t dqss (nom) nop
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 31 ?2003 micron technology, inc. figure 21: nonconsecutive write to write note: 1. di b , etc. = data-in for column b , etc. 2. three subsequent elements of data-in are a pplied in the specified order following di b . 3. three subsequent elements of data-in are a pplied in the specified order following di n . 4. a burst of 4 is shown. 5. each write command may be to any bank. 6. write latency set to 3. ck command write nop nop nop nop nop nop address bank, col b write bank, col n dq dm di n di b t dqss (nom) don?t care transitioning data ck ck# t0 t1 t2 t3 t4 t5 t4n wdqs t3n t6 t7 t6n t5n
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 32 ?2003 micron technology, inc. figure 22: random write cycles note: 1. di b , etc. = data-in for column b , etc. 2. b ', etc. = the next data-in following di b , etc., according to the specified burst order. 3. programmed burst length = 4 cases shown. 4. each write command may be to any bank. 5. last write command will have the rest of the nibble on t8 and t8 n . 6. write latency is set to 3. t0 t1 t2 t3 t4 t5 t4n ck ck# wdqs t3n t6 t7 t6n t5n t dqss (nom) command write nop write write nop nop nop address bank, col b bank, col g nop dq dm di b di b+1 di b+2 di b+3 di x di x+1 di x+2 di x+3 di g di g+1 don?t care transitioning data bank, col x
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 33 ?2003 micron technology, inc. figure 23: write to read note: 1. di b = data-in for column b . 2. three subsequent elements of data-in are a pplied in the specified order following di b . 3. a burst of 4 is shown. 4. t wtr is referenced from the first positive ck edge after the last nibble. 5. the read and write commands are to the same device. however, the read and write commands may be to different devices, in which case, t wtr is not required and the read command could be applied earlier. 6. a8 is low with the write command (auto precharge is disabled). 7. write latency is set to 3. 8. the 4 n prefetch architecture requires a 2-clock write-to-read turnaround time ( t wtr). t dqss (nom) ck ck# command write nop nop nop nop nop nop nop address bank a , col b nop t0 t1 t2 t3 t4n t4 t5 wdqs t3n t6 t7 t15 t16 t16n t wtr dq dm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) read bank a , col n cl = 8 di b di n t dqss ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) wdqs t dqss (min) dq dm cl = 8 di b di n t dqss ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) wdqs t dqss (max) dq dm don?t care transitioning data cl = 8 di b di n t dqss ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) rdqs rdqs rdqs ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 34 ?2003 micron technology, inc. figure 24: write to read with data masking note: 1. di b = data-in for column b . 2. one subsequent elements of data-in is a pplied in the specified order following di b . 3. a burst of 4 is shown. 4. t wtr is referenced from the first positive ck edge after the last nibble (as if the whole nibble is being written). 5. the read and write commands are to the same device. however, the read and write commands may be to different devices, in which case, t wtr is not required and the read command could be applied earlier. 6. a8 is low with the write command (auto precharge is disabled). 7. write latency is set to 3. 8. the 4 n prefetch architecture requires a 2-clock write-to-read turnaround time ( t wtr). t dqss (nom) ck ck# command write nop nop nop nop nop nop nop address bank a , col b nop t0 t1 t2 t3 t4n t4 t5 wdqs t3n t6 t7 t15 t16 t16n t wtr dq dm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) read bank a , col n cl = 8 di b di n t dqss ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) wdqs t dqss (min) dq dm cl = 8 di b di n t dqss ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) wdqs t dqss (max) dq dm don?t care transitioning data cl = 8 di b di n t dqss ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) rdqs rdqs rdqs ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 35 ?2003 micron technology, inc. figure 25: write to read?odd number of data masking note: 1. di b = data-in for column b . 2. a burst of 4 is shown. 3. t wtr is referenced from the first positive ck edge after the last nibble (as if the whole nibble is being written). 4. the read and write commands are to the same device. however, the read and write commands may be to different devices, in which case, t wtr is not required and the read command could be applied earlier. 5. a8 is low with the write command (auto precharge is disabled). 6. write latency is set to 3. 7. the 4 n prefetch architecture requires a 2-clock write-to-read turnaround time ( t wtr). t dqss (nom) ck ck# command write nop nop nop nop nop nop nop address bank a , col b nop t0 t1 t2 t3 t4n t4 t5 wdqs t3n t6 t7 t15 t16 t16n t wtr dq dm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) read bank a , col n cl = 8 di b di n t dqss ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) wdqs t dqss (min) dq dm cl = 8 di b di n t dqss ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) wdqs t dqss (max) dq dm don?t care transitioning data cl = 8 di b di n t dqss ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) rdqs rdqs rdqs ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 36 ?2003 micron technology, inc. figure 26: write to precharge note: 1. di b = data-in for column b . 2. three subsequent elements of data-in are a pplied in the specified order following di b . 3. a burst of 4 is shown. 4. a8 is low with the write command (auto precharge is disabled). 5. write latency is set to 3. 6. the 4 n prefetch architecture requires a 2-clock write-to-read turnaround time ( t wtr). t dqss (nom) ck ck# command write nop nop nop nop nop nop address bank a , col b nop t0 t1 t2 t3 t4n t4 t5 wdqs wdqs wdqs t3n t8 t9 t10 t wr dq dm t dqss (min) dq dm t dqss (max) dq dm don?t care transitioning data di b t dqss di b t dqss di b t dqss pre bank, ( a or all ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 37 ?2003 micron technology, inc. figure 27: write to prec harge ? with data masking note: 1. di b = data-in for column b . 2. one subsequent element of data-in is a pplied in the specified order following di b . 3. a burst of 4 is shown. 4. t wr is referenced from the first positive ck edge after the last nibble (as if the whole nibble is being written). 5. a8 is low with the write command (auto precharge is disabled). 6. write latency is set to 3. 7. the 4 n prefetch architecture requires a 2-clock write-to-read turnaround time ( t wtr). t dqss (nom) ck ck# command write nop nop nop nop nop nop address bank a , col b nop t0 t1 t2 t3 t4n t4 t5 wdqs wdqs wdqs t3n t8 t9 t10 t wr dq dm t dqss (min) dq dm t dqss (max) dq dm don?t care transitioning data di b t dqss di b t dqss di b t dqss pre bank, ( a or all ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 38 ?2003 micron technology, inc. figure 28: write to precharge ? odd number of data masking note: 1. di b = data-in for column b . 2. a burst of 4 is shown. 3. t wtr is referenced from the first positive ck edge after the last nibble (as if the whole nibble is being written). 4. a8 is low with the write command (auto precharge is disabled). 5. write latency is set to 3. t dqss (nom) ck ck# command write nop nop nop nop nop nop address bank a , col b nop t0 t1 t2 t3 t4n t4 t5 wdqs wdqs wdqs t3n t8 t9 t10 t wr dq dm t dqss (min) dq dm t dqss (max) dq dm don?t care transitioning data di b t dqss di b t dqss di b t dqss pre bank, ( a or all ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 39 ?2003 micron technology, inc. precharge the precharge command (shown in figure 29, precharge command) is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the pre- charge command is issued. input a8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. power-down (cke not active) unlike sdr sdrams, gddr3 sdrams require cke to be active at all times that an access is in progress: from the issuing of a read or write command until completion of the burst. for reads, a burst comple- tion is defined when the read postamble is satisfied; for writes, a burst completion is defined when the write postamble is satisfied. power-down (shown in figure 30, power-down, on page40) is entered when cke is registered low. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power- down occurs when there is a row active in any bank, this mode is referred to as active power-down. enter- ing power-down deactivates the input and output buffers, excluding ck, ck# and cke. for maximum power savings, the user also has the option of disabling the dll prior to entering power-down. in that case, the dll must be enabled and reset after exiting power- down, and 200 clock cycles must occur before a read command can be issued. however, power-down dura- tion is limited by the refresh requirements of the device, so in most applications, the self refresh mode is preferred over the dll-disabled power-down mode. while in power-down, cke low and a stable clock signal must be maintained at the inputs of the gddr3 sdram, while all other input signals are ?don?t care.? the power-down state is synchronously exited when cke is registered high (in conjunction with a nop or deselect command). a valid executable command may be applied four or fourteen clock cycles later. figure 29: precharge command cs# we# cas# ras# cke a8 ba0, 1 high all banks one bank ba a0?a7, a9?a11 ck ck# ba = bank address (if a8 is low; otherwise ?don?t care?) don?t care
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 40 ?2003 micron technology, inc. figure 30: power-down note: 1. cke n is the logic state of cke at clock edge n ; cke n -1 was the state of cke at the previous clock edge. 2. current state is the state of the gddr3 sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n , and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. deselect or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of 200 clock cycles is needed for the dll to lock before applying a read command if the dll was disabled. t is t is no read/write access in progress exit power-down mode t pdix enter power-down mode cke ck ck# command nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop nop valid t0 t1 t2 ta0 ta1 ta2 ta5/ta14 valid don?t care table 8: truth table ? cke notes: 1?4 cke n-1 cke n current state command n action n notes ll power-down x maintain power-down ll self refresh x maintain self refresh lh power-down deselect or nop exit power-down lh self refresh deselect or nop exit self refresh 5 hl all banks idle deselect or nop precharge power-down entry hl bank(s) active deselect or nop active power-down entry hl all banks idle auto refresh self refresh entry hh see truth table 3
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 41 ?2003 micron technology, inc. note: 1. this table applies when cke n -1 was high and cke n is high (see truth table 2) and after t xsnr has been met (if the pre- vious state was self refresh). 2. this table is bank-specific, except where noted (i.e., the cu rrent state is for a specific bank and the commands shown are those allowed to be issued to that bank when in th at state). exceptions are covered in the notes below. 3. all states and sequences not shown are illegal or reserved. 4. not bank-specific; requires that all banks are idle, and bursts are not in progress. 5. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 6. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 7. requires appropriate dm masking. 8. a write command may be applied after the completion of the read burst. 9. current states with read or write with auto-precharge enabled the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defined as if the same burst was executed with auto prec harge disabled and then followed with the earliest pos- sible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when t wr ends, with t wr measured as if auto precharge was disabled. the access period starts with registration of the command and ends where the precharge period (or t rp) begins. during the precharge period of the read with auto pr echarge enabled or write with auto precharge enabled states, active, precharge, read, and write commands to the other bank may be applied. in either case, all other related limitations apply (e.g., contention betw een read data and write data must be avoided). the minimum delay from a read or write command with auto precharge enabled to a command to a different bank is shown in table 10. table 9: truth table ? current state bank n ? command to bank n note: 1?3; notes appear below table current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) lhhh no operation (nop/continue previous operation) llhh active (select and activate row) idle l l l h auto refresh 4 llll load mode register 4 row active lhlh read (select column and start read burst) 6 lhl l write (select column and start write burst) 6 llhl precharge (deactivate row in bank or banks) 5 read (auto precharge disabled) lhlh read (select column and start new read burst) 6 lhl l write (select column and start write burst) 6, 8 llhl precharge (only after the read burst is complete 5 write (auto precharge disabled) lhlh read (select column and start read burst) 6, 7 lhl l write (select column and start new write burst) 6 llhl precharge (only after the write burst is complete) 5, 7
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 42 ?2003 micron technology, inc. note: cl = cas latency (cl) rounded up to the next integer. bl = burst length. wl = write latency. table 10: minimum delay between commands to different banks with auto precharge enabled from command to command minimum delay (with concurrent auto precharge) write with auto precharge read or read with auto precharge [wl + (bl/2)] t ck + t wtr write or write with auto precharge (bl/2) t ck precharge 1 t ck active 1 t ck read with auto precharge read or read with auto precharge (bl/2) * t ck write or write with auto precharge [cl + (bl/2) + 1 - wl] * t ck precharge 1 t ck active 1 t ck
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 43 ?2003 micron technology, inc. current states for truth tables: table 9 and table 11 idle the bank has been precharged, and t rp has been met. row active a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read a read burst has been initiated, with auto pre- charge disabled. write a write burst has been initiated, with auto pre- charge disabled. same-bank noninterruptible states the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and truth table 3, and according to truth table 4. precharging it starts with registration of a precharge com- mand and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating it starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the ?row active? state. read with auto precharge enabled this starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write with auto precharge enabled this starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. noninterruptible states the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing starts with registration of an auto refresh com- mand and ends when t rc is met. once t rfc is met, the gddr3 sdram will be in the all banks idle state. accessing mode register this starts with registration of a load mode reg- ister command and ends when t mrd has been met. once t mrd is met, the gddr3 sdram will be in the all banks idle state. precharging all it starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. read or write starts with the registration of the active command and ends with the last valid data nibble.
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 44 ?2003 micron technology, inc. note: 1. this table applies when cke n -1 was high and cke n is high (see truth table 2) and after t xsnr has been met (if the pre- vious state was self refresh). 2. this table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m , assuming that bank m is in such a state that the given command is allowable). 3. auto refresh and load mode register commands may only be issued when all banks are idle. 4. all states and sequences not shown are illegal or reserved. 5. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 6. requires appropriate dm masking. table 11: truth table ? current state bank n ? command to bank m notes: 1?4; notes appear below and on next page current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) lhh h no operation (nop/continue previous operation) idle x x x x any command otherwise allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhl h read (select column and start read burst) 5 lhl l write (select column and start write burst) 5 llh l precharge read (auto precharge disabled) llhh active (select and activate row) lhl h read (select column and start new read burst) 5 lhl l write (select column and start write burst) 5 llh l precharge write (auto precharge disabled) llhh active (select and activate row) lhl h read (select column and start read burst) 5, 6 lhl l write (select column and start new write burst) 5 llh l precharge read (with auto precharge) llhh active (select and activate row) lhl h read (select column and start new read burst) 5 lhl l write (select column and start write burst) 5 llh l precharge write (with auto precharge) llhh active (select and activate row) lhl h read (select column and start read burst) 5 lhl l write (select column and start new write burst) 5 llh l precharge
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 45 ?2003 micron technology, inc. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd supply relative to vss .......................................... -0.5v to +2.5v voltage on v dd q supply relative to vss ..........................................-0.5v to +2.5v voltage on v ref and inputs relative to vss ..........................................-0.5v to +2.5v voltage on i/o pins relative to vss ............................... -0.5v to v dd q +0.5v max junction temperature, t j ........................... +125c storage temperature (plastic) ...............-55c to +150c power dissipation......................................................tbd short circuit output current .................................50ma table 12: dc electrical characteristics and operating conditions notes: 1?5, 16, 40; notes appear on pages 51?53; 0 c t c 85 c; v dd = +1.8v 0.100v, v dd q = +1.8v 0.100v parameter/condition symbol min max units notes supply voltage v dd 1.7 1.9 v 32, 45 i/o supply voltage v dd q1.7 1.9 v 45 i/o reference voltage v ref 0.69 x v dd q0.71 x v dd qv 6 input high (logic 1) voltage v ih (dc) v ref + 0.15 v 28 input low (logic 0) voltage v il (dc) v ref - 0.15 v 28 input leakage current any input 0v v in v dd (all other pins not under test = 0v) i i -5 5 a output leakage current (dqs are disabled; 0v v out v dd q) i oz -5 5 a output logic low v ol (dc) 0.76 v table 13: ac input operating notes: 1?5, 16, 40; notes appear on pages 51?53; 0 c t c 85 c; v dd = +1.8v 0.100v, v dd q = +1.8v 0.100v parameter/condition symbol min max units notes input high (logic 1) voltage; dq v ih (ac) v ref + 0.250 ? v 14, 28, 39 input low (logic 0) voltage; dq v il (ac) ? v ref - 0.250 v 14, 28, 39 clock input differential voltage; ck and ck# v id (ac) 0.5 v dd q + 0.5 v 8 clock input crossing point voltage; ck and ck# v ix (ac) v ref - 0.15 v ref + 0.15 v 9
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 46 ?2003 micron technology, inc. figure 31: v dd q input voltage waveform 1.010v 1.110v 1.235v 1.242v 1.260v 1.278v 1.285v 1.410v 1.510v v il (ac) v il (dc) v ref - ac noise v ref - dc error v ref + dc error v ref + ac noise v ih (dc) v ih (ac) v oh (min) v in (ac) - provides margin between v ol (max) and v il ( ac) 0.420v v dd q (1.7v minimum) v ol (max) system noise margin (power/ground, cross talk, signal integrity attenuation) note: 1. numbers in diagram reflect nomimal values utilizing circuit below.
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 47 ?2003 micron technology, inc. note: 1. max operating case temperature; t c is measured in the center of the package, see figure below. 2. a thermal solution must be designed to ensure the dram device does not exceed the maximum t c during operation. 3. device functionality is not guaranteed if the dram device exceeds the maximum t c during operation. 4. the thermal resistance data is based on a number of sample s from multiple lots and should be viewed as a typical num- ber. f igure 32: tc test point table 14: thermal characteristics parameter/condition power symbol value units notes operating case temperature <1w t c 0?90 c 1, 2, 3 1w?2w t c 0?85 c 1, 2, 3 2w?3w t c 0?80 c 1, 2, 3 junction to case (top) jc tbd c/w 4 6.50mm 1 3.00mm 12.00mm 6.00mm t c test poi nt table 15: clock input operating conditions notes: 1?5, 15, 16, 30; notes appear on pages 51?53; 0oc t c 85 c; v dd = +1.8v 0.100v, v dd q = +1.8v 0.100v parameter/condition symbol min max units notes clock input midpoint voltage; ck and ck# v mp (dc) 1.16 1.36 v 6, 9 clock input voltage level; ck and ck# v in (dc) 0.42 v dd q + 0.3 v 6 clock input differential voltage; ck and ck# v id (dc) 0.22 v dd qv6, 8 clock input differential voltage; ck and ck# v id (ac) 0.5 v dd q + 0.5 v 8 clock input crossing point voltage; ck and ck# v ix (ac) v ref - 0.15 v ref + 0.15 v 9
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 48 ?2003 micron technology, inc. figure 33: clock input note: 1. this provides a minimum of 1.16v to a maximum of 1.36v, and is always 70% of v dd q. 2. ck and ck# must cross in this region. 3. ck and ck# must meet at least v(dc) min when static and is centered around v mp (dc). 4. ck and ck# must have a minimum 600mv peak-to-peak swing. 5. ck or ck# may not be more positive than v dd q + 0.5v or lower than 0.22v. 6. for ac operation, all dc clock requirements must also be satisfied. 7. numbers in diagram reflect nominal values. ck# ck 2.3v 5 maximum clock level minimum clock level 5 0.22v 1.26v 1.36v 1.16v v id (ac) 4 v id (dc) 3 x v mp (dc) 1 v ix (ac) 2 x table 16: capacitance note: 13; notes appear on pages 51?53 parameter symbol min max units notes delta input/output capacitance: dqs, dqs, dm dc io ?0.20pf 24 delta input capacitance: command and address dc i 1 ?0.40pf 29 delta input capacitance: ck, ck# dc i 2 ?0.20pf 29 input/output capacitance: dqs, dqs, dm c io 3.5 4.5 pf input capacitance: command and address c i 1 3.0 4.0 pf input capacitance: ck, ck# c i 2 3.0 4.0 pf input capacitance: cke c i 3 3.0 4.0 pf
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 49 ?2003 micron technology, inc. ta bl e 1 7 : i dd specifications and conditions notes: 1?5, 10, 12, 14, 40; notes on pages 51?53; 0oc t c 85oc; v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v max parameter/condition symbol -16 -18 -2 units notes operating current: one bank; active precharge; t rc = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle; wl = 4 rc (min) i dd 0 tbd tbd tbd ma 22, 46 operating current: one bank; active read precharge; burst = 4; t rc (min); t ck = t ck (min); i rc = out = 0ma; address and control inputs changing once per clock cycle; wl = 4 i dd 1 tbd tbd tbd ma 22, 46 precharge power-down standby current: all banks idle; power-down mode; t ck = t ck min; cke = low i dd 2p tbd tbd tbd ma 32 idle standby current: cs# = high; all banks idle; t ck = t ck (min); cke = high; inputs changing once per clock cycle i dd 2n tbd tbd tbd ma active power-down standby current: one bank active; power-down mode; t ck = t ck (min); cke = low; wl=4 i dd 3p tbd tbd tbd ma 32 active standby current: cs# = high; cke = high; one bank; active precharge; t rc = t ras (max); t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle i dd 3n tbd tbd tbd ma 22 operating current: burst = 4; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); i out = 0ma; wl = 4 i dd 4r tbd tbd tbd ma operating current: burst = 4; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck = t ck (min); dq, dm, and dqs inputs changing twice per clock cycle; wl = 4 i dd 4w tbd tbd tbd ma 46 auto refresh current t rfc (min) i dd 5a tbd tbd tbd ma 22 t rfc = 7.8s i dd 5b tbd tbd tbd ma 27 self refresh current: cke 0.2v i dd 6 tbd tbd tbd ma 11
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 50 ?2003 micron technology, inc. table 18: electrical characteristics and ac operating conditions notes: 1-5,14-16, 33, 40; notes on pages 51?53; 0 c t c 85 c; v dd = +1.8v 0.1v, v ddq = +1.8v 0.1v ac characteristics -16 -18 -2 units notes parameter symbol min max min max min max access window of rdqs from ck/ck# t ac -0.25 +0.25 -0.25 +0.25 -0.25 +0.25 t ck ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 30 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 30 clock cycle time cl = 8 t ck(8) 1.66 3.3 ? ? ? ? ns 33, 40 cl = 7 t ck(7) 1.81 3.3 1.81 3.3 ? ? ns 33, 40 cl = 6 t ck(6) 2.00 3.3 2.00 3.3 2.00 3.3 ns 33, 40 cl = 5 t ck(5) ? ? 2.5 3.3 2.5 3.3 ns 33, 40 write latency t wl242414 t ck 43 dq and dm input hold time relative to dqs t dh 0.225 0.25 0.25 ns 26, 31 dq and dm input setup time relative to dqs t ds 0.225 0.25 0.25 ns 26, 31 active termination setup time t ats 10 10 10 ns active termination hold time t ath 10 10 10 ns dqs input high pulse width t dqsh 0.48 0.52 0.48 0.52 0.48 0.52 t ck dqs input low pulse width t dqsl 0.48 0.52 0.48 0.52 0.48 0.52 t ck dqs-dq skew t dqsq -0.160 0.160 -0.190 0.190 -0.225 0.225 ns 25, 26 write command to first dqs latching transition t dqss wl - 0.25 wl + 0.25 wl - 0.25 wl + 0.25 wl - .025 wl + 0.25 t ck dqs falling edge to ck rising ? setup time t dss 0.25 0.25 0.25 t ck dqs falling edge from ck rising ? hold time t dsh 0.25 0.25 0.25 t ck half strobe period t hp t dqsh, t dqsl t dqsh, t dqsl t dqsh, t dqsl ns 34 data-out high-impedance window from ck/ ck# t hz -0.3 -0.3 -0.3 ns 18 data-out low-impedance window fromck/ ck# t lz -0.3 -0.3 -0.3 ns 18 address and control input hold time t ih 0.45 0.5 0.5 ns 14 address and control input setup time t is 0.45 0.5 0.5 ns 14 address and control input pulse width t ipw 1.2 1.3 1.3 ns load mode register command cycle time t mrd 4 4 4 t ck 44 data valid output window t dv t dqhp - 0.32ns t dqhp - 0.38ns t dqhp - 0.45ns ns 25, 26, 34 active to precharge command t ras 35 120,000 36 120,000 36 120,000 ns 35 active to active/auto refresh command period t rc 52 52 52 ns auto refresh command period t rfc 60 60 60 ns refresh to refresh command interval` t refc 70 70 70 s 23 average periodic refresh interval t refi 7.8 7.8 7.8 s 23 active to read delay t rcdr 16 16 16 ns active to write delay t rcdw 12 12 12 ns precharge command period t rp 14.4 14.4 16 ns dqs read preamble t rpre 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 6 6 6 ns exit power-down t pdix 4 + t is 4 + t is 4 + t is t ck dqs write preamble t wpre 0.4 0.6 0.4 0.6 0.4 0.6 t ck 47 dqs write preamble setup time t wpres 0 0 0 ns 20, 21 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 19, 37 write recovery time t wr 4 4 4 t ck internal write to read command delay t wtr 3 3 3 t ck exit self refresh to non-read command t xsnr 66 66 66 t ck exit self refresh to read command t xsrd 200 200 200 t ck
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 51 ?2003 micron technology, inc. notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load: 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.0v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci- fications are guaranteed for the specified ac input levels under normal use conditions. the mini- mum slew rate for the input signals used to test the device is 3 v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level specifications are a pseudo open drain design for improved high- speed signaling. 6. v ref is expected to equal 70 percent of v dd q for the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed 2 percent of the dc value. thus, from 70% of v dd q, v ref is allowed 25mv for dc error and an additional 25mv for ac noise. 7. reserved for future use. 8. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 9. the value of v ix is expected to equal 70 percent of v dd q for the transmitting device and must track variations in the dc level of the same. 10. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time at minimum cas latency and does not include the on-die termination current. outputs are open during i dd measurements. 11. enables on-chip refresh and address counters. 12. i dd specifications are tested after the device is properly initialized. 13. this parameter is sampled. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, v ref = v ss , f = 500 mhz, t a = 25c, v out (dc) = 0.75v, v dd q, v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, reflecting the fact that they are matched in load- ing. 14. command/address input slew rate = 3 v/ns. if the slew rate is less than 3 v/ns, timing is no longer referenced to the midpoint but to the v il (ac) maximum and v ih (ac) minimum points. 15. the ck/ck# input reference level (for timing ref- erenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 16. inputs are not recognized as valid until v ref sta- bilizes. exception: during the period before v ref stabilizes, mf, cke 0.3 x v dd q is recognized as low. 17. reserved for future use. 18. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific volt- age level, but specify when the device output is no longer driving (hz) or begins driving (lz). 19. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. it is recommended that wdqs be valid (high or low) on or before the write command. 22. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras max for i dd measurements is the largest multiple of t ck that meets the maximum absolute value for t ras. 23. the refresh period is 4k every 32ms. this equates to an average refresh rate of 7.8s. 24. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 25. the valid data window is derived by achieving other specifications ? t dqhp and t dqsq, [ t dqhp - 0.32ns (-16), t dqhp - 0.38ns (-18), t dqhp - 0.45ns (-2)]. the data valid window derates in direct proportion to the strobe duty cycle and a practical data valid window can be derived. the strobe is allowed a maximum duty cycle variation of 48:52. functionality is uncertain when operat- ing beyond a 48:52 ratio. the data valid window derating curves are provided below for duty cycles 4pf 240 ? 60 ? z = 60 ? o zq gddr3 1.26v v ref v dd q
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 52 ?2003 micron technology, inc. ranging between 50:50 and 48:52, based off the optional read strobe. 26. referenced to each output group: rdqs0 with dq0?dq7, rdqs1 with dq8?dq15, rdqs2 with dq16?dq23, and rdqs with dq24?dq31. 27. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period ( t rfc [min]) else cke is low (e.g., during standby). 28. the dc values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid level. the inputs require the ac value to be achieved during signal transition edge, and the driver should achieve the same slew rate through the ac values. 29. the input capacitance per pin group will not dif- fer by more than this maximum amount for any given device. 30. ck and ck# input slew rate must be 3 v/ns. 31. dq and dm input slew rates must not deviate from wdqs by more than 10 percent. if the dq/ dm/wdqs slew rate is less than 3 v/ns, timing is no longer referenced to the midpoint but to the v il (ac) maximum and v ih (ac) minimum points. 32. v dd must not vary more than 4 percent if cke is not active while any bank is active. 33. the clock is allowed up to 90ps of jitter. each timing parameter is allowed to vary by the same amount. 34. t hp (min) is the lesser of t dqsl minimum and t dqsh minimum actually applied to the device ck and ck# inputs, collectively during bank active. 35. for reads and writes with auto precharge the gddr3 device will hold off the internal pre- charge command until t ras (min) has been satisfied. figure 34: derating data valid window ( t qh - t dqsq) 0.480 0.472 0.464 0.456 0.448 0.550 0.540 0.530 0.520 0.510 0.3 0.4 0.4 0.5 0.5 0.6 0.6 50/50 49.5/50.5 49/51 48.5/52.5 48/52 dqs duty cycle ns -16 @ tck =1.6ns -2 @ tck = 2ns -18 @ tck = 1.8ns
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 53 ?2003 micron technology, inc. 36. programmable drive curves 40 example: a) the full variation in driver pull-down current from minimum to maximum process, tempera- ture and voltage will lie within the outer bounding lines of the v-i curve of figure 35, pull-down characteristics. b) the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 35, pull-down characteristics. c)the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 36, pull-up characteristics. d)the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 36, pull-up characteristics. 37. the last rising edge of wdqs after the write post- amble must be driven high by the controller. wdqs cannot be pulled high by the on-die ter- mination alone. for the read postamble the gddr3 will drive the last rising edge of the read postamble. 38. the voltage levels used are derived from the refer- enced test load. in practice, the voltage levels obtained from a properly terminated bus will pro- vide significantly different voltage values. 39. v ih overshoot: v ih (max) = v dd q + 0.5v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. v il under- shoot: v il (min) = 0.0v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. 40. the dll must be reset when changing the fre- quency, followed by 200 clock cycles. 41. junction temperature is a function of total device power dissipation and device mounting environ- ment. measured per semi g38-87. 42. the thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. these parameters are not tested in production. 43. the write latency can be set from 1 to 4 clocks but can never be less than 2ns for latencies of 1 and 2 clocks. when the write latency is set to 1 or 2 clocks, the input buffers are always on, reduc- ing the latency but adding power. when the write latency is set to 3 or 4 clocks the input buffers are turned on during the write com- mands for lower power operation and can never be less than 5ns. 44. a minimum of 14 clock cycles is required after the load mode register (lmr) command before a read command can be issued. 45. v dd , v ref , and v dd q must track. 46. setting the write latency to 1 or 2 clocks will increase the operating current by xma. 47. a low-to-high transition on the wdqs line is not allowed in the half clock cycle prior to the write preamble. figure 35: pull-down characteristics figure 36: pull-up characteristics 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v out ( v) nomin al low high -50.00 -45.00 -40.00 -35.00 -30.00 -25.00 -20.00 -15.00 -10.00 -5.00 0.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v dd q - v out (v) i out (ma) nomin al low high
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 54 ?2003 micron technology, inc. table 19: programmed drive characteristics at 40 voltage (v) pull-down current (ma) pull-up current (ma) nominal minimum maximum nominal minimum maximum 0.1 2.77 2.32 3.04 -2.93 -2.44 -3.27 0.2 5.44 4.56 5.98 -5.75 -4.79 -6.42 0.3 8.02 6.70 8.82 -8.46 -7.03 -9.45 0.4 10.49 8.75 11.56 -11.05 -9.18 -12.37 0.5 12.86 10.71 14.19 -13.52 -11.23 -15.17 0.6 15.12 12.57 16.72 -15.87 -13.17 -17.83 0.7 17.27 14.35 19.14 -18.10 -15.01 -20.37 0.8 19.31 16.03 21.44 -20.21 -16.74 -22.78 0.9 21.24 17.63 23.61 -22.18 -18.37 -25.04 1.0 23.04 19.13 25.66 -24.03 -19.90 -27.17 1.1 24.74 20.55 27.57 -25.77 -21.34 -29.17 1.2 26.38 21.94 29.39 -27.42 -22.72 -31.04 1.3 27.99 23.31 31.16 -29.03 -24.07 -32.85 1.4 29.59 24.67 32.91 -30.62 -25.40 -34.62 1.5 31.18 26.03 34.65 -32.21 -26.73 -36.37 1.6 32.77 27.38 36.38 -33.78 -28.06 -38.11 1.7 34.36 28.73 38.11 -35.35 -29.37 -39.85 1.8 35.94 ? 39.83 -36.92 ? -41.58 1.9 - ? 41.55 ? ? -43.30 table 20: programmed drive characteristics at 60 for active termination voltage (v) pull-up current (ma) nominal minimum maximum 0.1 -1.95 -1.63 -2.18 0.2 -3.83 -3.19 -4.28 0.3 -5.64 -4.69 -6.30 0.4 -7.36 -6.12 -8.25 0.5 -9.01 -7.49 -10.11 0.6 -10.58 -8.78 -11.89 0.7 -12.07 -10.01 -13.58 0.8 -13.47 -11.16 -15.18 0.9 -14.79 -12.25 -16.70 1.0 -16.02 -13.27 -18.12 1.1 -17.18 -14.23 -19.44 1.2 -18.28 -15.14 -20.70 1.3 -19.35 -16.04 -21.90 1.4 -20.41 -16.94 -23.08 1.5 -21.47 -17.82 -24.25 1.6 -22.52 -18.70 -25.41 1.7 -23.57 -19.58 -26.56 1.8 -24.61 ? -27.72 1.9 ? ? -28.87
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 55 ?2003 micron technology, inc. figure 37: active termination characteristics figure 38: data output timing ? t dqsq, t qh, and data valid window note: 1. t dqsq represents the skew between the eight dq lines and the respective rdqs pin. 2. t dqsq is derived at each rdqs edge and is not cumulative over time and begins with first dq transition and ends with the last valid transition of dq. 3. t ac is shown in the nominal case. 4. t dqhp is the lesser of t dqsl or t dqsh strobe transition collectively when a bank is active. 5. the data valid window is derived for each rdqs transitions and is defined by t dv. 6. there are four rdqs pins for this device with rdqs0 in re lation to dq(0?7), rdqs1 in relation dq(8?15), rdqs2 in rela- tion to dq(16?24), and rdqs3 in relation to dq(25?31). 7. this diagram only represents one of the four byte lanes. -35.00 -30.00 -25.00 -20.00 -15.00 -10.00 -5.00 0.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 v dd q - v out (v ) i out (ma) nominal low high t dv 3 t ch t cl t dqsq 2 (min) t dqsq 2 (min) t dqsq 2 (max) t dqsq 2 (max) t dqsh 4 t dqsl 4 rdqs 1,6 dq (last data valid) dq (first data no longer valid) all dqs and rdqs, collectively 5 ck ck# t1 t0 t2 t3 t4 t2n t3n t2 t2 t2n t2n t3n t3 t3 t3n t dv 3 t dv 3 t dv 3 t2 t2n t3 t3n
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 56 ?2003 micron technology, inc. figure 39: data output timing ? t ac note: 1. t ac represents the relationship between dq, rdqs to the crossing of ck and ck#. figure 40: data input timing note: 1. t dsh (min) generally occurs during t dqss (min). 2. t dss (min) generally occurs during t dqss (max). t ch t ac (max) t cl ck ck# t1 t0 t2 t3 t4 t2n t3n t dqsh 4 t dqsl 4 rdqs 1, 6 all dqs and rdqs, collectively 5 t2 t2n t3n t3 rdqs 1, 6 all dqs and rdqs, collectively 5 t2 t2n t3n t3 t ac (min) t dqsh 4 t dqsl 4 t dh t ds dm dq ck ck# t0 t1 t1n t2 t2n t3 di b wdqs don?t care transitioning data t dqsh t dqsl t dss 2 t dsh 1 t dsh 1 t dss 2
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 57 ?2003 micron technology, inc. figure 41: initialize and load mode registers note: 1. a dll reset with a8 = h is required after enabling the dll. 2. t mrd is required before any command can be applied, and 200 cycles of ck are required before a read command can be issued. 3. the two auto refresh commands at tc0 and td0 may be applied after the load mode register command at ta0. 4. pre = precharge command, lmr = load mode register command, ar = auto refresh command, act = active command, ra = row address, ba = bank address. 5. dq[0:7] will be driving the vendor id and die rev id when the res pin is in a logic low state prior to the first rising edge of res during power-up. cke cke dq ba0, ba1 200 cycles of ck 2 load extended mode register load mode register 1 t mrd t mrd t rp t rfc t rfc t is t ath power-up: v dd and ck stable t = 200s t = 10ns t rp high t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0-a7, a9-a11 ra a8 ra all banks ck res ck# t ats t ch t cl v ref v dd v dd q command 6 lmr nop pre lmr ar ar act t is t ih ba0 = h, ba1 = l t is t ih t is t ih ba0 = l, ba1 = l t is t ih ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) code code t is t ih code code ( ) ( ) ( ) ( ) pre all banks t is t ih ( ) ( ) ( ) ( ) t0 t1 ta0 tb0 tc0 td0 te0 tf0 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don?t care ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) wdqs high ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) rdqs high ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 58 ?2003 micron technology, inc. figure 42: power-down mode note: 1. if this command is a precharge (or if the device is alread y in the idle state), then the power-down mode shown is pre- charge power-down. if this command is an active (or if at least one row is already active), then the power-down mode shown is active power-down. 2. no column accesses are allowed to be in progress at the time power-down is entered. ck ck# command valid 1 nop addr cke dq dm rdqs, wdqs nop valid t ck t ch t cl t is t is t ih t is t is t ih t ih t is enter 2 power-down mode exit power-down mode ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 ta0 ta1 ta3 t2 nop don?t care ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) valid valid t pdix ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 59 ?2003 micron technology, inc. figure 43: auto refresh mode note: 1. pre = precharge, act = active, ar = auto refresh, ra = row address, ba = bank address. 2. nop commands are shown for ease of illustration; other valid commands may be possible at these times. 3. ?don?t care? if a8 is high at this point; a8 must be high if mo re than one bank is active (i.e., must precharge all active banks). 4. dm, dq, and dqs signals are all ?don?t care?/high-z for operations shown. 5. the second auto refresh is not required and is only show n as an example of two back-to-back auto refresh com- mands. ck ck# command 1 nop 2 valid valid nop 2 nop 2 pre cke ra a 0?a7, a9?a11 a8 1 ba0, ba1 1 bank(s) 3 ba ar nop 2 ar 5 rdqs wdqs nop 2 act nop 2 one bank all banks t ck t ch t cl t is t is t ih t ih t is t ih ra ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq 4 dm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rfc 5 t rp t rfc t0 t1 t2 t3 t4 ta0 tb0 ta1 tb1 tb2 don?t care ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 60 ?2003 micron technology, inc. figure 44: self refresh mode note: 1. clock must be stable before exiting self refresh mode. 2. device must be in the all banks idle state prior to entering self refresh mode. 3. t xsnr is required before any non-read command can be applied, and t xsrd (200 cycles of ck) is required before a read command can be applied. 4. ar = auto refresh command. ck 1 ck# command 4 nop ar addr cke 1 valid dq dm wdqs rdqs valid nop t rp 2 t ch t cl t ck t is t xsnr/ t xsrd 3 t is t ih t is t is t ih t ih t is enter self refresh mode exit self refresh mode ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 ta0 tb0 ta1 ( ) ( ) ( ) ( ) ( ) ( ) don?t care ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 61 ?2003 micron technology, inc. figure 45: bank read without auto precharge note: 1. do n = data-out from column n ; subsequent elements are provided in the programmed order. 2. burst length = 4 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a8 is high at t5. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustration; other commands may be valid at these times. 7. the precharge command can be applied as early as t5 if t ras minimum is met. ck ck# cke a8 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras 7 t rc t rp cl = 8 dm t0 t1 t2 t3 t10 t11 t11n t12n t12 t13 t14 dq 1 rdqs case 1: t ac (min) case 2: t ac (max) dq 1 rdqs t rpre t rpst t ac (min) t hz (max) do n do n nop 6 nop 6 command 5 3 act ra ra col n read 2 pre 7 bank x ra ra ra bank x bank x 4 act bank x nop 6 nop 6 nop 6 t hz (min) one bank all banks don?t care transitioning data a0?a7, a9 a10?a11 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rpre t lz (min) t lz (max) ( ) ( ) ( ) ( ) t rpst
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 62 ?2003 micron technology, inc. figure 46: bank read with auto precharge note: 1. do n = data-out from column n ; subsequent elements are provided in the programmed order. 2. burst length = 4 in the case shown. 3. enable auto precharge. 4. act = active, ra = row address, ba = bank address. 5. nop commands are shown for ease of illustration; other commands may be valid at these times. 6. the read command can be applied even if t ras (min) has not been met by t5; the device will hold off the precharge command until t ras (min) is met. ck ck# cke a8 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras 6 t rc t rp cl = 8 dm t0 t1 t2 t3 t10 t11 t11n t12n t12 t13 t14 dq 1 rdqs case 1: t ac (min) case 2: t ac (max) dq 1 rdqs t rpre t rpst t rpst t ac (min) t ac (max) t lz (min) t lz (max) do n do n nop 5 nop 5 command 4 3 act ra ra col n read 2 nop 5 bank x ra ra ra bank x act bank x nop 5 nop 5 nop 5 t hz (min) don?t care transitioning data a0?a7, a9 a10?a11 t rpre t hz (max)
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 63 ?2003 micron technology, inc. figure 47: bank write without auto precharge note: 1. di n = data-in to column n ; subsequent elements are provided in the specified order. 2. burst length = 4 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a8 is high at t3. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustration; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 8. t dss is applicable during t dqss (max) and is referenced from ck t5 or t6. 9. write latency is set to one. ck ck# wdqs cke a8 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras t dsh 7 t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t9 t10 t4n nop 6 nop 6 command 5 3 act ra ra col n write 2 nop 6 one bank all banks bank x pre bank x nop 6 nop 6 nop 6 t dqsl t dqsh t dss 8 bank x 4 dq 1 dm di b t ds t dh don?t care transitioning data t dqss (nom) a0?a7, a9 a10?a11 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 64 ?2003 micron technology, inc. figure 48: bank write with auto precharge note: 1. di n = data-in to column n ; subsequent elements are provided in the specified order. 2. burst length = 4 in the case shown. 3. enable auto precharge. 4. act = active, ra = row address, ba = bank address 5. nop commands are shown for ease of illustration; other commands may be valid at these times. 6. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 7. t dss is applicable during t dqss (max) and is referenced from ck t5 or t6. 8. write latency is set to one. ck ck# wdqs cke a8 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras t dsh 6 t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t9 t10 t4n nop 5 nop 5 command 4 3 act ra ra col n write 2 nop 5 bank x bank x nop 5 nop 5 nop 5 nop 5 t dqsl t dqsh t dss 7 dq 1 dm di b t ds t dh don?t care transitioning data t dqss (nom) a0-a7, a9 a10-a11 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice. gddr3_2.fm - rev. a 6/03 en 65 ?2003 micron technology, inc. figure 49: write ? dm operation note: 1. di n = data-in to column n ; subsequent elements are provided in the specified order. 2. burst length = 4 in the case shown. 3. disable auto precharge. 4. ?don?t care? if a8 is high at t3. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustration; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 8. t t dss is applicable during t dqss (max) and is referenced from ck t5 or t6. 9. t ds and t dh are referenced to wdqs. 10.write latency is set to one. ck ck# wdqs cke a8 ba0, ba1 t ck t ch t cl t is t is t ih t is t is t ih t ih t ih t is t ih ra t rcd t ras t dsh 7 t rp t wr t0 t1 t2 t3 t4 t5 t5n t6 t9 t10 t4n nop 6 nop 6 command 5 3 act ra ra col n write 2 nop 6 one bank all banks bank x pre bank x nop 6 nop 6 nop 6 t dqsl t dqsh t dss 8 t dsh 7 t dss 8 bank x 4 dq 1 dm di b t ds t dh don?t care transitioning data t dqss (nom) a0?a7, a9 a10?a11 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x32 gddr3 sdram advance 09005aef808f8a4f micron technology, inc., reserves the right to change products or specifications without notice.. gddr3_2.fm - rev. a 6/03 en 66 ?2003 micron technology, inc ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. figure 50: 135-ball fbga note: all dimensions are in millimeters. data sheet designation advance : this datasheet contains initial descript ions of products still under development. ball a1 id 0.850 0.075 seating plane 0.10 c c c 1.20 max ball a11 ball a1 id 1.00 typ 0.80 typ 5.00 0.05 10.00 4.00 ball a1 12.00 0.10 6.00 0.05 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ? 0.40 135x ? 0.45 solder ball material: eutectic 63% sn, 37% pb or 62% sn, 36% pb, 2% ag solder ball pad: ? 0.33mm mold compound: epoxy novolac substrate: plastic laminate 11.20 5.60 0.05 6.50 0.05 13.00 0.10 c l c l

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